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www.irf.com 1 09/15/03 IRLR3717 irlu3717 hexfet power mosfet notes through are on page 11 benefits very low r ds(on) at 4.5v v gs ultra-low gate impedance fully characterized avalanche voltage and current applications high frequency synchronous buck converters for computer processor power high frequency isolated dc-dc converters with synchronous rectification for telecom and industrial use absolute maximum ratings parameter units v ds drain-to-source voltage v v gs gate-to-source voltage i d @ t c = 25c continuous drain current, v gs @ 10v a i d @ t c = 100c continuous drain current, v gs @ 10v i dm pulsed drain current p d @t c = 25c maximum power dissipation w p d @t c = 100c maximum power dissipation linear derating factor w/c t j operating junction and c t stg storage temperature range soldering temperature, for 10 seconds thermal resistance parameter typ. max. units r jc junction-to-case ??? 1.69 c/w r ja junction-to-ambient (pcb mount) ??? 50 r ja junction-to-ambient ??? 110 300 (1.6mm from case) -55 to + 175 89 0.59 44 max. 120 81 460 20 20 d-pak IRLR3717 i-pak irlu3717 v dss r ds(on) max qg 20v 4.0m 21nc

2 www.irf.com s d g static @ t j = 25c (unless otherwise specified) parameter min. typ. max. units bv dss drain-to-source breakdown voltage 20 ??? ??? v ? v dss / ? t j breakdown voltage temp. coefficient ??? 12 ??? mv/c r ds(on) static drain-to-source on-resistance ??? 3.4 4.0 m ? ??? 4.6 5.5 v gs(th) gate threshold voltage 1.55 2.0 2.45 v ? v gs(th) / ? t j gate threshold voltage coefficient ??? -6.4 ??? mv/c i dss drain-to-source leakage current ??? ??? 1.0 a ??? ??? 150 i gss gate-to-source forward leakage ??? ??? 100 na gate-to-source reverse leakage ??? ??? -100 gfs forward transconductance 49 ??? ??? s q g total gate charge ??? 21 31 q gs1 pre-vth gate-to-source charge ??? 6.4 ??? q gs2 post-vth gate-to-source charge ??? 1.9 ??? nc q gd gate-to-drain charge ??? 7.2 ??? q godr gate charge overdrive ??? 5.5 ??? see fig. 16 q sw switch charge (q gs2 + q gd ) ??? 9.1 ??? q oss output charge ??? 13 ??? nc t d(on) turn-on delay time ??? 14 ??? t r rise time ??? 14 ??? ns t d(off) turn-off delay time ??? 5.8 ??? t f fall time ??? 16 ??? c iss input capacitance ??? 2830 ??? c oss output capacitance ??? 920 ??? pf c rss reverse transfer capacitance ??? 420 ??? avalanche characteristics parameter units e as single pulse avalanche energy mj i ar avalanche current a e ar repetitive avalanche energy mj diode characteristics parameter min. typ. max. units i s continuous source current ??? ??? 120 (body diode) a i sm pulsed source current ??? ??? 460 (body diode) v sd diode forward voltage ??? ??? 1.0 v t rr reverse recovery time ??? 22 33 ns q rr reverse recovery charge ??? 13 19 nc t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by ls+ld) v gs = 20v v gs = -20v conditions 8.9 max. 460 12 ? = 1.0mhz conditions v gs = 0v, i d = 250a reference to 25c, i d = 1ma v gs = 10v, i d = 15a v ds = v gs , i d = 250a v ds = 16v, v gs = 0v v ds = 16v, v gs = 0v, t j = 125c clamped inductive load v ds = 10v, i d = 12a v ds = 10v, v gs = 0v v dd = 10v, v gs = 4.5v i d = 12a v ds = 10v t j = 25c, i f = 12a, v dd = 10v di/dt = 100a/s t j = 25c, i s = 12a, v gs = 0v showing the integral reverse p-n junction diode. mosfet symbol v gs = 4.5v, i d = 12a ??? v gs = 4.5v typ. ??? ??? i d = 12a v gs = 0v v ds = 10v
www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.1 1 10 100 v ds , drain-to-source voltage (v) 1.0 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 20s pulse width tj = 175c 2.5v vgs top 10v 6.0v 4.5v 4.0v 3.5v 3.0v 2.8v bottom 2.5v 0 2 4 6 8 v gs , gate-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( ) t j = 25c t j = 175c v ds = 25v 20s pulse width -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 30a v gs = 10v 0.1 1 10 100 v ds , drain-to-source voltage (v) 0.01 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 10v 6.0v 4.5v 4.0v 3.5v 3.0v 2.8v bottom 2.5v 20s pulse width tj = 25c 2.5v
4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 0 5 10 15 20 25 30 q g total gate charge (nc) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 16v v ds = 10v i d = 12a 0.0 0.5 1.0 1.5 2.0 2.5 v sd , source-to-drain voltage (v) 1.00 10.00 100.00 1000.00 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 0 1 10 100 1000 v ds , drain-to-source voltage (v) 1 10 100 1000 10000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 1msec 10msec operation in this area limited by r ds (on) 100sec tc = 25c tj = 175c single pulse 1 10 100 v ds , drain-to-source voltage (v) 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss
www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature fig 10. threshold voltage vs. temperature 25 50 75 100 125 150 175 t c , case temperature (c) 0 25 50 75 100 125 i d , d r a i n c u r r e n t ( a ) limited by package -75 -50 -25 0 25 50 75 100 125 150 175 200 t j , temperature ( c ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v g s ( t h ) g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a 1e-006 1e-005 0.0001 0.001 0.01 0.1 1 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc ri (c/w) i (sec) 0.771 0.000430 0.629 0.006491 0.291 0.072119 j j 1 1 2 2 3 3 r 1 r 1 r 2 r 2 r 3 r 3 c ci= i / ri ci= i / ri
6 www.irf.com d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13. gate charge test circuit fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as fig 12c. maximum avalanche energy vs. drain current r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v v gs fig 14a. switching time test circuit fig 14b. switching time waveforms v gs v ds 90% 10% t d(on) t d(off) t r t f v gs pulse width < 1s duty factor < 0.1% v dd v ds l d d.u.t + - 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 500 1000 1500 2000 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 8.2a 9.7a bottom 12a
www.irf.com 7 fig 15. for n-channel hexfet power mosfets
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? ? p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period

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8 www.irf.com control fet

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#' p loss = p conduction + p switching + p drive + p output this can be expanded and approximated by; p loss = i rms 2 r ds(on ) () + i q gd i g v in f ? ? ? ? ? ? + i q gs 2 i g v in f ? ? ? ? ? ? + q g v g f () + q oss 2 v in f ? ? ? ? " (

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synchronous fet the power loss equation for q2 is approximated by; p loss = p conduction + p drive + p output * p loss = i rms 2 r ds(on) () + q g v g f () + q oss 2 v in f ? ? ? ? ? + q rr v in f ( ) *dissipated primarily in q1. for the synchronous mosfet q2, r ds(on) is an im- portant characteristic; however, once again the im- portance of gate charge must not be overlooked since it impacts three critical areas. under light load the mosfet must still be turned on and off by the con- trol ic so the gate drive losses become much more significant. secondly, the output charge q oss and re- verse recovery charge q rr both generate losses that are transfered to q1 and increase the dissipation in that device. thirdly, gate charge will impact the mosfets? susceptibility to cdv/dt turn on. the drain of q2 is connected to the switching node of the converter and therefore sees transitions be- tween ground and v in . as q1 turns on and off there is a rate of change of drain voltage dv/dt which is ca- pacitively coupled to the gate of q2 and can induce a voltage spike on the gate that is sufficient to turn the mosfet on, resulting in shoot-through current . the ratio of q gd /q gs1 must be minimized to reduce the potential for cdv/dt turn on. power mosfet selection for non-isolated dc/dc converters figure a: q oss characteristic
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6.73 (.265) 6.35 (.250) - a - 4 1 2 3 6.22 (.245) 5.97 (.235) - b - 3x 0.89 (.035) 0.64 (.025) 0.25 (.010) m a m b 4.57 (.180) 2.28 (.090) 2x 1.14 (.045) 0.76 (.030) 1.52 (.060) 1.15 (.045) 1.02 (.040) 1.64 (.025) 5.46 (.215) 5.21 (.205) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 6.45 (.245) 5.68 (.224) 0.51 (.020) min. 0.58 (.023) 0.46 (.018) lead assignments 1 - gate 2 - drain 3 - source 4 - drain 10.42 (.410) 9.40 (.370) notes: 1 dimensioning & tolerancing per ansi y14.5m, 1982. 2 controlling dimension : inch. 3 conforms to jedec outline to-252aa. 4 dimensions shown are before solder dip, solder dip max. +0.16 (.006). example: lot code 9u1p this is an irfr120 with assembly we e k = 16 dat e code year = 0 logo rectifier international as s e mb l y lot code 016 irf u120 9u 1p notes : t his part marking information applies to devices produced before 02/26/2001 international logo rectifier 34 12 irfu120 916a lot code as s e mb l y example: wi t h as s e mb l y this is an irfr120 year 9 = 1999 dat e code line a we e k 16 in the as sembly line "a" as s e mbled on ww 16, 1999 lot code 1234 part number notes : t his part marking information applies to devices produced after 02/26/2001
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6.73 (.265) 6.35 (.250) - a - 6.22 (.245) 5.97 (.235) - b - 3x 0.89 (.035) 0.64 (.025) 0.25 (.010) m a m b 2.28 (.090) 1.14 (.045) 0.76 (.030) 5.46 (.215) 5.21 (.205) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) lead assignments 1 - gate 2 - drain 3 - source 4 - drain notes: 1 dimensioning & tolerancing per ansi y14.5m, 1982. 2 controlling dimension : inch. 3 conforms to jedec outline to-252aa. 4 dimensions shown are before solder dip, solder dip max. +0.16 (.006). 9.65 (.380) 8.89 (.350) 2x 3x 2.28 (.090) 1.91 (.075) 1.52 (.060) 1.15 (.045) 4 1 2 3 6.45 (.245) 5.68 (.224) 0.58 (.023) 0.46 (.018) week = 16 dat e code year = 0 notes : t hi s part mar ki ng i nfor mati on appl i es to devi ces produced before 02/26/2001 example: lot code 9u1p this is an irfr120 with assembly as s e mb l y international rect ifier logo lot code irf u120 9u 1p 016 international logo rect ifier lot code as s e mb l y example: with assembly this is an irfr120 ye ar 9 = 1999 dat e code line a we e k 19 in the assembly line "a" as s embled on ww 19, 1999 lot code 5678 part number notes : t his part marking information applies to devices produced after 02/26/2001 56 irf u120 919a 78
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- . tr 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) 12.1 ( .476 ) 11.9 ( .469 ) feed direction feed direction 16.3 ( .641 ) 15.7 ( .619 ) trr trl notes : 1. controlling dimension : millimeter. 2. all dimensions are shown in millimeters ( inches ). 3. outline conforms to eia-481 & eia-541. notes : 1. outline conforms to eia-481. 16 mm 13 inch data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 09/03
repetitive rating; pulse width limited by max. junction temperature. starting t j = 25c, l = 6.4mh, r g = 25 ? , i as = 12a. pulse width 400s; duty cycle 2%. calculated continuous current based on maximum allowable junction temperature. package limitation current is 30a. when mounted on 1" square pcb (fr-4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994.

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